)]}'
{
  "commit": "28318d11027a46b2c8a549423e83198bafe316bb",
  "tree": "971798d7cc1e63bf937dd434b8ede70b1ca4dbde",
  "parents": [
    "ba6f521d0d9401f518f99b547d248c31d021fa71"
  ],
  "author": {
    "name": "Barret Rhoden",
    "email": "brho@cs.berkeley.edu",
    "time": "Thu Mar 28 15:40:43 2019 -0400"
  },
  "committer": {
    "name": "Barret Rhoden",
    "email": "brho@cs.berkeley.edu",
    "time": "Thu Mar 28 15:48:16 2019 -0400"
  },
  "message": "x86: Try to fix MP table I/O interrupt assignment entries\n\nI have a desktop PC with two IOAPICs, 8 and 9, and the IOINTR entries do\nnot specify valid APIC IDs (0 and 2).  ACPI agrees the IOAPIC ids are 8\nand 9.\n\nThis method works at least for the lower IOAPIC (id \u003d 8) on my deskop.\n\nYou\u0027d have to have broken MP tables to even get this far.  Prior to this\ncommit, PCI devices would complain about not being able to set up an IOAPIC\nroute.\n\nThese changes will make those busted IOINTRs appear to be correct ones,\nbut there\u0027s no guarantee that the hardware is actually wired that way.\nmight think you\u0027re using an IOAPIC route when you\u0027re actually using the\nwrong one.\n\nSigned-off-by: Barret Rhoden \u003cbrho@cs.berkeley.edu\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "caa9009d71c9d054fee8ddd8f3c3086fb71b3cc0",
      "old_mode": 33188,
      "old_path": "kern/arch/x86/mp.c",
      "new_id": "7d51f365829f9a9d1ab689e5312e1e6c98c2a2d3",
      "new_mode": 33188,
      "new_path": "kern/arch/x86/mp.c"
    }
  ]
}