commit f2889d5fce2d042f8bbed1b6c868421a896e184f
author Aditya Basu <mitthu@google.com> Fri Aug 16 12:34:07 2019 -0400
committer Barret Rhoden <brho@cs.berkeley.edu> Mon Aug 19 12:39:09 2019 -0400
tree c5e171c3aa05c335d15f6c2875674f27984355c0
parent 0e92ede84cf810359c01b4aa25748081c3ca1fbb

pci: add mmio addr to #pci ctl files

Before:
    $ cat /dev/pci/0.4.0ctl
    8.80.0 8086/2021  11 0:0x 16384

After:
    $ cat /dev/pci/0.4.0ctl
    8.80.0 8086/2021  11 0:0x    0/febf0000 16384

The mmio_base32 and mmio_base64 physical address mappings are now
printed. If the device is dma64 capable then it gets mapped to
mmio_base64 as is the case above. The PCI device information shown above
is for Intel CBDMA.

Signed-off-by: Aditya Basu <mitthu@google.com>
Signed-off-by: Barret Rhoden <brho@cs.berkeley.edu>

kern/drivers/dev/pci.c

diff --git a/kern/drivers/dev/pci.c b/kern/drivers/dev/pci.c
index 73fe9d9..c062676 100644
--- a/kern/drivers/dev/pci.c
+++ b/kern/drivers/dev/pci.c
@@ -168,8 +168,9 @@
 		for (i = 0; i < COUNT_OF(p->bar); i++) {
 			if (p->bar[i].mmio_sz == 0)
 				continue;
-			w = seprintf(w, ebuf, " %d:%.8lux %d", i,
-				     p->bar[i].pio_base, p->bar[i].mmio_sz);
+			w = seprintf(w, ebuf, " %d:%.8lux %4x/%8x %d", i,
+				     p->bar[i].pio_base, p->bar[i].mmio_base32,
+				     p->bar[i].mmio_base64, p->bar[i].mmio_sz);
 		}
 		*w++ = '\n';
 		*w = '\0';