)]}'
{
  "commit": "f2889d5fce2d042f8bbed1b6c868421a896e184f",
  "tree": "c5e171c3aa05c335d15f6c2875674f27984355c0",
  "parents": [
    "0e92ede84cf810359c01b4aa25748081c3ca1fbb"
  ],
  "author": {
    "name": "Aditya Basu",
    "email": "mitthu@google.com",
    "time": "Fri Aug 16 12:34:07 2019 -0400"
  },
  "committer": {
    "name": "Barret Rhoden",
    "email": "brho@cs.berkeley.edu",
    "time": "Mon Aug 19 12:39:09 2019 -0400"
  },
  "message": "pci: add mmio addr to #pci ctl files\n\nBefore:\n    $ cat /dev/pci/0.4.0ctl\n    8.80.0 8086/2021  11 0:0x 16384\n\nAfter:\n    $ cat /dev/pci/0.4.0ctl\n    8.80.0 8086/2021  11 0:0x    0/febf0000 16384\n\nThe mmio_base32 and mmio_base64 physical address mappings are now\nprinted. If the device is dma64 capable then it gets mapped to\nmmio_base64 as is the case above. The PCI device information shown above\nis for Intel CBDMA.\n\nSigned-off-by: Aditya Basu \u003cmitthu@google.com\u003e\nSigned-off-by: Barret Rhoden \u003cbrho@cs.berkeley.edu\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "73fe9d9f88cc1fd3263ce2e8712af214faaa9a0a",
      "old_mode": 33188,
      "old_path": "kern/drivers/dev/pci.c",
      "new_id": "c06267653774d9cf72beb2c8b9063f986e49a1f2",
      "new_mode": 33188,
      "new_path": "kern/drivers/dev/pci.c"
    }
  ]
}